The dynamic component that is incurred, whenever signals in a circuit undergo logic transition, often dominates power dissipation in VLSI circuits. In practice, a large fraction of such transitions incurred during the operation of commonly used circuits are unnecessary. Such transitions have no bearing on the result computed by the circuit.
It can be reasonably concluded that not all parts of a circuit may need to function during each clock cycle. Some components may be idle in some clock cycles. Recognizing this fact, several low power design techniques have been proposed that are based on suppressing or eliminating unnecessary signal transitions. The term power management is used to refer to such techniques in general. Applying power management to a design typically involves two steps:
Identifying idle conditions for various parts of the circuit. PA1 Redesigning the circuit to eliminate switching activity in idle components, therefore avoiding unnecessary power dissipation in those parts. PA1 Clock Gating: Gating of clock signals to save power consumed in the clock network and registers L. Benini, P. Siegel, and G. DeMicheli, "Saving power by synthesizing gated clocks for sequential circuits," IEEE Design & Test of Computers, pp. 32-41 (Winter 1994) and L. Benini and G. DeMicheli, Automatic synthesis of gated-clock sequential circuits," IEEE Trans. Computer-Aided Design, vol. 15, pp. 630-643 (June 1996). PA1 Pre-computation: Disabling registers from loading to save power consumption in the registers and the combinational logic fed by the registers M. Aldina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation-based sequential logic optimization for low power," IEEE Trans. VLSI Systems, vol. 2, pp. 426-436 (December 1994). PA1 Operand Isolation: Inserting transparent latches at the inputs of an embedded combinational logic block, and additional control circuitry to detect idle conditions for the logic block 16, 7, 8]. The outputs of the control circuitry are used appropriately to disable the latches at the inputs of the logic block from changing values. Thus, the previous cycles input values are retained at the inputs of the logic block under consideration, eliminating unnecessary power dissipation. PA1 Controller-based power management: Re-designing the control logic of a circuit such that the power consumption due to unnecessary switching activity in the data path is minimized A. Raghunathan, S. Dey, and N. K. Jha, "Power management techniques for control-flow, p intensive designs," Proc. Design Automation Conf., pp. 429-434 (June 1997). PA1 An abundance of smaller components like multiplexers dominate power consumption, while functional units may account for a small part of the total power. See A. Raghunathan, S. Dey, and N. K. Jha, "Glitch analysis and reduction in register-transfer-level power optimization," in Proc. Design Automation Conf., pp. 331-336, June 1996. The power overhead due to inserting transparent latches is comparable to power savings obtained when power management is applied to sub-circuits such as multiplexer networks. PA1 The signals that detect idle conditions for various sub-circuits are typically late-arriving (for example, due to the presence of nested conditionals within each controller state, the idle conditions may depend on outputs of comparators from the data path). Therefor, the timing constraints that must be imposed to apply conventional power management techniques (the enable signal to the transparent latches must settle before its data inputs can change) are often not met. PA1 The presence of significant glitching activity at control as well as data path signals needs to be accounted for to obtain maximal power savings. See A. Raghunathan, S. Dey, and N. K. Jha, "Glitch analysis and reduction in register-transfer-level power optimization," in Proc. Design Automation Conf., pp. 331-336, June 1996.
Power management is frequently deployed by designers of power-constrained systems and is arguably one of the most commonly used low power design techniques. See J. Rabaey and M. Pedram (Editors), Low Power Design Methodologies., Kluwer Academic Publishers, Norwell, Mass., (1996). It is desirable to have power management incorporated into automatic synthesis tools as well.
Many modern microprocessors have adopted the strategy of gating the clock input to registers and other circuit blocks to suppress unnecessary transitions in the clock signal as well as in the circuit block under consideration. See A. Correale, "Overview of power minimization techniques employed in the IBM PowerPC 4xx embedded processors, Proc. Int. Symp. Low Power Design, pp. 75-80 (April 1995). Automated synthesis techniques to apply clock gating and maximize its efficiency have been also been known. See G. Tellez A. Farrahi, and M. Sarrafzadeh, "Activity driven clock design for low power circuits.", Proc. Int. Conf. Computer-Aided Design, pp.62-65, (November 1995) and L. Benini, P. Siegel, and G. De Micheli, "Saving power by synthesizing gated clocks for sequential circuits", IEEE Design & Test of Computers, pp. 32-41, (Winter 1994).
Recently, high-level synthesis techniques for power management have been proposed. See E. Musoll and J. Cortadella, "High-level synthesis techniques for reducing the activity of functional units", Proc. Int. Symp. Low Power Design, pp. 99-104, (April 1995); J. Monteiro, S. Devadas, P. Ashar, and A. Mauskar, "Scheduling techniques to enable power management", Proc. Design Automation Conf., pp. 349-352 (June 1996) and A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi, "Power management techniques for control-flow intensive designs", Proc. Design Automation Conf. pp. 429-434 (June 1997). A scheduling algorithm that aims to maximize the idle times for functional units was presented in J. Monteiro, S. Devadas, P. Ashar, and A. Mauskar, "Scheduling techniques to enable power management", Proc. Design Automation Conf., pp. 349-352 (June 1996).
A controller respecification technique, based on redesigning the controller logic to reduce the activity in the components of the data path was presented in A. Raghunathan, S. Dey, N. K. Jha, and K. Wakabayashi, "Power management techniques for control-flow intensive designs, Proc. Design Automation Conf., pp. 429-434 (June 1997). Techniques geared toward maximizing the "sleep times" of storage elements, such as registers and memories were presented in A. Farrahi, G. Tellez and M. Sarrafzadeh, "Memory segmentation to exploit sleep mode operation", Proc. Design Automation Conf., pp.36-41 (June 1995). At the logic level, two successful power management techniques, based on guarded evaluation and pre-computation have been presented. See V. Tiwari and S. Malik, "Guarded evaluation: Pushing power management to logic level synthesis design, Proc. Int. Symp. Low Power Design, pp. 221-226 (April 1995) and M. Aldina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou, "Precomputation based sequential logic optimization for low power", IEEE Trans. VLSI Systems, vol. 2, pp. 426-436.
Guarded evaluation identifies logic cones that can be shut down under certain input conditions. These logic cones are "guarded" by latches, which are disabled, thus preventing the logic cone from consuming power, when the output of the cone does not influence the circuit output. In precomputation a simple combinational circuit, called the precomputation circuit, is added to the original circuit. Under some input conditions, the precomputation logic shuts down the original circuit and itself computes the outputs.
Several conventional techniques have been used to reduce power consumption in a circuit by eliminating unnecessary logic transitions at various signals within the circuit. The term "power management" is collectively used to refer to these techniques.
High-level synthesis (also called behavioral synthesis) converts a behavioral description of a VLSI circuit into a structural, register-transfer level (RTL) implementation described as an interconnection of macro blocks (e.g., functional units, registers, multiplexers, buses, memory blocks, etc.), and random logic.
A behavioral description of a sequential circuit contains an algorithmic specification of its functionality. Such a description may contain almost no information about the cycle-by-cycle behavior of the circuit or its structural implementation. Behavioral synthesis tools typically compile a behavioral description into a suitable intermediate format, such as Control-Data Flow Graph (CDFG). Vertices in the CDFG represent various operations of the behavioral description. Data and control edges are used to represent data dependencies between operations and the flow of control.
High-level synthesis tools typically perform one or more of the following tasks: transformation, module selection, clock selection, scheduling, resource allocation and assignment (also called resource sharing or hardware sharing). Scheduling determines the cycle-by-cycle behavior of the design by assigning each operation to one or more clock cycles or control steps. Allocation decides the number of hardware resources of each type that will be used to implement the behavioral description. Assignment refers to the binding of each variable (and the corresponding operation) to one of the allocated registers (and the corresponding functional units).
Register sharing or assignment refers to a process of mapping each variable in the behavioral description of a sequential circuit to a register in its RTL implementation. A comprehensive survey on high-level synthesis techniques can be found in R. Camposano and W. Wolf, High-Level VLSI Synthesis. Kluwer Academic Publishers, Norwell, Mass., 1991 and D. D. Gajski, N. D. Dutt, A. C.-H. Wu, and S. Y.-L. Lin, High-level Synthesis: Introduction to Chip and System Design. Kluwer Academic Publishers, Norwell, Mass., 1992.
Automatic sequential circuit power management methodologies have been proposed that use the following techniques: